#include <rtthread.h>
#include <drivers/ofw.h>
#include <drivers/misc.h>
#include <drivers/core/dm.h>
#include <mmu.h>
#include <mm_page.h>
#include <bitmap.h>

Include dependency graph for dma.h:

Data Structures
struct	rt_dma_slave_config

struct	rt_dma_slave_transfer

struct	rt_dma_controller

struct	rt_dma_controller_ops

struct	rt_dma_chan

struct	rt_dma_pool

struct	rt_dma_map_ops

Macros
#define	RT_DMA_F_LINEAR RT_BIT(0)

#define	RT_DMA_F_32BITS RT_BIT(1)

#define	RT_DMA_F_NOCACHE RT_BIT(2)

#define	RT_DMA_F_DEVICE RT_BIT(3)

#define	RT_DMA_F_NOMAP RT_BIT(4)

#define	RT_DMA_F_WT RT_BIT(5)

#define	RT_DMA_PAGE_SIZE ARCH_PAGE_SIZE

Enumerations
enum	rt_dma_transfer_direction { RT_DMA_MEM_TO_MEM , RT_DMA_MEM_TO_DEV , RT_DMA_DEV_TO_MEM , RT_DMA_DEV_TO_DEV , RT_DMA_DIR_MAX }

enum	rt_dma_slave_buswidth { RT_DMA_SLAVE_BUSWIDTH_UNDEFINED = 0 , RT_DMA_SLAVE_BUSWIDTH_1_BYTE = 1 , RT_DMA_SLAVE_BUSWIDTH_2_BYTES = 2 , RT_DMA_SLAVE_BUSWIDTH_3_BYTES = 3 , RT_DMA_SLAVE_BUSWIDTH_4_BYTES = 4 , RT_DMA_SLAVE_BUSWIDTH_8_BYTES = 8 , RT_DMA_SLAVE_BUSWIDTH_16_BYTES = 16 , RT_DMA_SLAVE_BUSWIDTH_32_BYTES = 32 , RT_DMA_SLAVE_BUSWIDTH_64_BYTES = 64 , RT_DMA_SLAVE_BUSWIDTH_128_BYTES = 128 , RT_DMA_SLAVE_BUSWIDTH_BYTES_MAX }

Functions
rt_inline void	rt_dma_controller_add_direction (struct rt_dma_controller *ctrl, enum rt_dma_transfer_direction dir)

rt_inline void	rt_dma_controller_set_addr_mask (struct rt_dma_controller *ctrl, rt_uint64_t mask)

rt_err_t	rt_dma_controller_register (struct rt_dma_controller *ctrl)

rt_err_t	rt_dma_controller_unregister (struct rt_dma_controller *ctrl)

rt_err_t	rt_dma_chan_start (struct rt_dma_chan *chan)

rt_err_t	rt_dma_chan_pause (struct rt_dma_chan *chan)

rt_err_t	rt_dma_chan_stop (struct rt_dma_chan *chan)

rt_err_t	rt_dma_chan_config (struct rt_dma_chan chan, struct rt_dma_slave_config conf)

rt_err_t	rt_dma_chan_done (struct rt_dma_chan *chan, rt_size_t size)

rt_err_t	rt_dma_prep_memcpy (struct rt_dma_chan chan, struct rt_dma_slave_transfer transfer)

rt_err_t	rt_dma_prep_cyclic (struct rt_dma_chan chan, struct rt_dma_slave_transfer transfer)

rt_err_t	rt_dma_prep_single (struct rt_dma_chan chan, struct rt_dma_slave_transfer transfer)

struct rt_dma_chan *	rt_dma_chan_request (struct rt_device dev, const char name)

rt_err_t	rt_dma_chan_release (struct rt_dma_chan *chan)

void *	rt_dma_alloc (struct rt_device dev, rt_size_t size, rt_ubase_t dma_handle, rt_ubase_t flags)

void	rt_dma_free (struct rt_device dev, rt_size_t size, void cpu_addr, rt_ubase_t dma_handle, rt_ubase_t flags)

rt_inline void *	rt_dma_alloc_coherent (struct rt_device dev, rt_size_t size, rt_ubase_t dma_handle)

rt_inline void	rt_dma_free_coherent (struct rt_device dev, rt_size_t size, void cpu_addr, rt_ubase_t dma_handle)

rt_err_t	rt_dma_sync_out_data (struct rt_device dev, void data, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags)

rt_err_t	rt_dma_sync_in_data (struct rt_device dev, void out_data, rt_size_t size, rt_ubase_t dma_handle, rt_ubase_t flags)

rt_inline rt_bool_t	rt_dma_device_is_coherent (struct rt_device *dev)

rt_inline void	rt_dma_device_set_ops (struct rt_device dev, const struct rt_dma_map_ops ops)

struct rt_dma_pool *	rt_dma_pool_install (rt_region_t *region)

rt_err_t	rt_dma_pool_extract (rt_size_t cma_size, rt_size_t coherent_pool_size)

Detailed Description

DMA (Direct Memory Access) controller framework public API.

Defines the DMA controller, channel, memory pool, and mapping operations interfaces. Provides APIs for controller registration, channel lifecycle management, transfer preparation (memcpy, cyclic, single), DMA buffer allocation with cache coherence management, and device tree integration.

Macro Definition Documentation

◆ RT_DMA_F_LINEAR

#define RT_DMA_F_LINEAR RT_BIT(0)

DMA pool: linear address space (all DMA pools have this flag)

◆ RT_DMA_F_32BITS

#define RT_DMA_F_32BITS RT_BIT(1)

DMA pool: limited to 32-bit addressable memory (below 4GB)

◆ RT_DMA_F_NOCACHE

#define RT_DMA_F_NOCACHE RT_BIT(2)

DMA allocation: use non-cacheable memory mapping.

◆ RT_DMA_F_DEVICE

#define RT_DMA_F_DEVICE RT_BIT(3)

DMA pool: device-private pool (matches pool->dev)

◆ RT_DMA_F_NOMAP

#define RT_DMA_F_NOMAP RT_BIT(4)

DMA allocation: do not map virtual address, return physical.

◆ RT_DMA_F_WT

#define RT_DMA_F_WT RT_BIT(5)

DMA allocation: use write-through cache mapping.

◆ RT_DMA_PAGE_SIZE

#define RT_DMA_PAGE_SIZE ARCH_PAGE_SIZE

DMA pool page size matches architecture page size.

Enumeration Type Documentation

◆ rt_dma_transfer_direction

enum rt_dma_transfer_direction

DMA transfer direction.

Defines the data flow direction for a DMA transfer. The controller's dir_cap bitmap indicates which directions are supported.

Enumerator
RT_DMA_MEM_TO_MEM	Memory-to-memory copy (no peripheral involved)
RT_DMA_MEM_TO_DEV	Memory to peripheral (TX / playback)
RT_DMA_DEV_TO_MEM	Peripheral to memory (RX / capture)
RT_DMA_DEV_TO_DEV	Device-to-device (rare, may not be supported)
RT_DMA_DIR_MAX	Sentinel: total number of direction types

◆ rt_dma_slave_buswidth

enum rt_dma_slave_buswidth

DMA slave bus width options.

Specifies the transfer width for source and destination on the DMA bus. Must match the peripheral's FIFO width for correct operation.

Enumerator
RT_DMA_SLAVE_BUSWIDTH_UNDEFINED	Undefined / not configured
RT_DMA_SLAVE_BUSWIDTH_1_BYTE	8-bit transfers
RT_DMA_SLAVE_BUSWIDTH_2_BYTES	16-bit transfers
RT_DMA_SLAVE_BUSWIDTH_3_BYTES	24-bit transfers
RT_DMA_SLAVE_BUSWIDTH_4_BYTES	32-bit transfers
RT_DMA_SLAVE_BUSWIDTH_8_BYTES	64-bit transfers
RT_DMA_SLAVE_BUSWIDTH_16_BYTES	128-bit transfers
RT_DMA_SLAVE_BUSWIDTH_32_BYTES	256-bit transfers
RT_DMA_SLAVE_BUSWIDTH_64_BYTES	512-bit transfers
RT_DMA_SLAVE_BUSWIDTH_128_BYTES	1024-bit transfers
RT_DMA_SLAVE_BUSWIDTH_BYTES_MAX	Sentinel: maximum bus width enum value

Function Documentation

◆ rt_dma_controller_add_direction()

rt_inline void rt_dma_controller_add_direction	(	struct rt_dma_controller *	ctrl,
		enum rt_dma_transfer_direction	dir
	)

Add a supported transfer direction to a DMA controller.

Controllers call this during probe to declare which directions they support.

Parameters

[in]	ctrl	DMA controller
[in]	dir	Transfer direction to add

◆ rt_dma_controller_set_addr_mask()

rt_inline void rt_dma_controller_set_addr_mask	(	struct rt_dma_controller *	ctrl,
		rt_uint64_t	mask
	)

Set the address mask for a DMA controller.

The mask defines the valid address range for DMA transfers. For example, RT_DMA_ADDR_MASK(32) limits transfers to the lower 4GB.

Parameters

[in]	ctrl	DMA controller
[in]	mask	Address bit mask

◆ rt_dma_controller_register()

rt_err_t rt_dma_controller_register ( struct rt_dma_controller * ctrl )

Register a DMA controller with the framework.

◆ rt_dma_controller_unregister()

rt_err_t rt_dma_controller_unregister ( struct rt_dma_controller * ctrl )

Unregister a DMA controller (fails if channels are in use)

◆ rt_dma_chan_start()

rt_err_t rt_dma_chan_start ( struct rt_dma_chan * chan )

Start a prepared DMA transfer on a channel.

◆ rt_dma_chan_pause()

rt_err_t rt_dma_chan_pause ( struct rt_dma_chan * chan )

Pause a running DMA transfer (falls back to stop if not supported)

◆ rt_dma_chan_stop()

rt_err_t rt_dma_chan_stop ( struct rt_dma_chan * chan )

Stop a running DMA transfer.

◆ rt_dma_chan_config()

rt_err_t rt_dma_chan_config	(	struct rt_dma_chan *	chan,
		struct rt_dma_slave_config *	conf
	)

Configure a DMA channel with slave-specific parameters.

◆ rt_dma_chan_done()

rt_err_t rt_dma_chan_done	(	struct rt_dma_chan *	chan,
		rt_size_t	size
	)

Signal transfer completion (called by controller ISR)

◆ rt_dma_prep_memcpy()

rt_err_t rt_dma_prep_memcpy	(	struct rt_dma_chan *	chan,
		struct rt_dma_slave_transfer *	transfer
	)

Prepare a memory-to-memory DMA transfer.

◆ rt_dma_prep_cyclic()

rt_err_t rt_dma_prep_cyclic	(	struct rt_dma_chan *	chan,
		struct rt_dma_slave_transfer *	transfer
	)

Prepare a cyclic (repeating) DMA transfer.

◆ rt_dma_prep_single()

rt_err_t rt_dma_prep_single	(	struct rt_dma_chan *	chan,
		struct rt_dma_slave_transfer *	transfer
	)

Prepare a single (one-shot) DMA transfer.

◆ rt_dma_chan_request()

struct rt_dma_chan* rt_dma_chan_request	(	struct rt_device *	dev,
		const char *	name
	)

Request a DMA channel for a slave device (by DT name or auto)

◆ rt_dma_chan_release()

rt_err_t rt_dma_chan_release ( struct rt_dma_chan * chan )

Release a DMA channel back to the controller.

◆ rt_dma_alloc()

void* rt_dma_alloc	(	struct rt_device *	dev,
		rt_size_t	size,
		rt_ubase_t *	dma_handle,
		rt_ubase_t	flags
	)

Allocate a DMA-capable memory buffer.

◆ rt_dma_free()

void rt_dma_free	(	struct rt_device *	dev,
		rt_size_t	size,
		void *	cpu_addr,
		rt_ubase_t	dma_handle,
		rt_ubase_t	flags
	)

Free a DMA buffer previously allocated with rt_dma_alloc()

◆ rt_dma_alloc_coherent()

rt_inline void* rt_dma_alloc_coherent	(	struct rt_device *	dev,
		rt_size_t	size,
		rt_ubase_t *	dma_handle
	)

Allocate a coherent (non-cacheable) DMA buffer.

Convenience wrapper around rt_dma_alloc() with RT_DMA_F_NOCACHE | RT_DMA_F_LINEAR.

Parameters

[in]	dev	DMA-capable device
[in]	size	Requested size in bytes
[out]	dma_handle	Physical DMA address

Returns: Kernel virtual address, or RT_NULL on failure

◆ rt_dma_free_coherent()

rt_inline void rt_dma_free_coherent	(	struct rt_device *	dev,
		rt_size_t	size,
		void *	cpu_addr,
		rt_ubase_t	dma_handle
	)

Free a coherent DMA buffer.

Parameters

[in]	dev	DMA-capable device
[in]	size	Buffer size in bytes
[in]	cpu_addr	Kernel virtual address
[in]	dma_handle	Physical DMA address

◆ rt_dma_sync_out_data()

rt_err_t rt_dma_sync_out_data	(	struct rt_device *	dev,
		void *	data,
		rt_size_t	size,
		rt_ubase_t *	dma_handle,
		rt_ubase_t	flags
	)

Synchronize CPU cache for DMA output (CPU → device)

◆ rt_dma_sync_in_data()

rt_err_t rt_dma_sync_in_data	(	struct rt_device *	dev,
		void *	out_data,
		rt_size_t	size,
		rt_ubase_t	dma_handle,
		rt_ubase_t	flags
	)

Synchronize CPU cache for DMA input (device → CPU)

◆ rt_dma_device_is_coherent()

rt_inline rt_bool_t rt_dma_device_is_coherent ( struct rt_device * dev )

Check if a device is DMA-coherent.

Reads the "dma-coherent" boolean property from the device's device tree node (if present).

Parameters

[in] dev Device to check

Returns: RT_TRUE if the device is DMA-coherent

◆ rt_dma_device_set_ops()

rt_inline void rt_dma_device_set_ops	(	struct rt_device *	dev,
		const struct rt_dma_map_ops *	ops
	)

Override the DMA mapping operations for a device.

Parameters

[in]	dev	Device to configure
[in]	ops	Custom DMA map operations (or NULL to reset)

◆ rt_dma_pool_install()

struct rt_dma_pool* rt_dma_pool_install ( rt_region_t * region )

Install a DMA memory pool from a region descriptor.

◆ rt_dma_pool_extract()

rt_err_t rt_dma_pool_extract	(	rt_size_t	cma_size,
		rt_size_t	coherent_pool_size
	)

Extract coherent pool and CMA from memblock reserved memory.

Data Structures

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ RT_DMA_F_LINEAR

◆ RT_DMA_F_32BITS

◆ RT_DMA_F_NOCACHE

◆ RT_DMA_F_DEVICE

◆ RT_DMA_F_NOMAP

◆ RT_DMA_F_WT

◆ RT_DMA_PAGE_SIZE

Enumeration Type Documentation

◆ rt_dma_transfer_direction

◆ rt_dma_slave_buswidth

Function Documentation

◆ rt_dma_controller_add_direction()

◆ rt_dma_controller_set_addr_mask()

◆ rt_dma_controller_register()

◆ rt_dma_controller_unregister()

◆ rt_dma_chan_start()

◆ rt_dma_chan_pause()

◆ rt_dma_chan_stop()

◆ rt_dma_chan_config()

◆ rt_dma_chan_done()

◆ rt_dma_prep_memcpy()

◆ rt_dma_prep_cyclic()

◆ rt_dma_prep_single()

◆ rt_dma_chan_request()

◆ rt_dma_chan_release()

◆ rt_dma_alloc()

◆ rt_dma_free()

◆ rt_dma_alloc_coherent()

◆ rt_dma_free_coherent()

◆ rt_dma_sync_out_data()

◆ rt_dma_sync_in_data()

◆ rt_dma_device_is_coherent()

◆ rt_dma_device_set_ops()

◆ rt_dma_pool_install()

◆ rt_dma_pool_extract()