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RT-Thread RTOS
An open source embedded real-time operating system
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Concrete BSP references (paths under **rt-thread/bsp/**).
pic-gicv2.c** during **rt_pic_init**interrupt-parent = <&gicv2>** + **GIC_SPI n type**rt_dm_dev_get_irq** → virtual IRQ → **rt_pic_attach_irq**PCIe **interrupt-map** on host points at **&gicv2 GIC_SPI 143…**.
Single interrupt line from GIC — no cascade. Shows standard DM consumer pattern.
| Piece | Detail |
|---|---|
| Root | PMIC **rk8xx->irq** from SoC GPIO |
| Child PIC | **rk8xx_irqchip**, **rt_pic_linear_irq** |
| Cascade | **rt_pic_cascade(pirq, rk8xx->irq)** in **rk8xx_irq_map** |
| Demux | Thread reads **status_base** regs → **rt_pic_handle_isr** |
| DT | **interrupts = <&rk8xx_intc 0>** on sub-devices |
Template for GPIO/PMIC expander IRQ chips.
| Piece | Detail |
|---|---|
| Child node | **legacy-interrupt-controller** (OFW child) |
| Child PIC | **rockchip_intx_ops**, 4 lines (**RT_PCI_INTX_PIN_MAX**) |
**rt_ofw_data(intx_np) = &intx_pic** | PCI **interrupt-map** targets this |
| Parent ISR | **rockchip_pcie_legacy_isr** on **legacy** GIC IRQ |
No RT_PIC_F_IRQ_ROUTING | Software poll of legacy status register |
PCI function drivers use **rt_pci_ofw_irq_parse_and_map** → maps through **intx_pic** → GIC.
Many drivers only use allocated virtual IRQ:
Examples: **i2c-rk3x.c**, **spi-rockchip.c**, **mailbox-rockchip.c**.
| Hardware | Pattern | Example |
|---|---|---|
| Single GIC line per device | **get_irq + attach** | UART, I2C |
| Aggregated status register | Child PIC + parent ISR poll | RK PCIe INTx |
| Many lines behind one pin | Child PIC + cascade | RK8xx PMIC |
| Message-signalled | MSI PIC + PCI | See PIC and PCI MSI |