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RT-Thread RTOS
An open source embedded real-time operating system
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Header: **components/drivers/include/drivers/nvmem.h**. Core: **components/drivers/nvmem/nvmem.c**.
NVMEM models OTP, eFuse, EEPROM slices, PMIC trim, MAC/calibration blobs as a provider device plus cells (named or indexed byte/bit ranges). Consumers resolve cells from device tree phandles—see NVMEM device model (DM).
There is no in-tree OTP driver under **components/drivers/nvmem/**; SoC providers live under **SOC_DM_NVMEM_DIR** in the BSP.
Use **rt_nvmem_*** when… | Use a dedicated driver when… |
|---|---|
| Multiple consumers need slices of one OTP/eFuse controller. | Only one driver reads a fixed offset once at boot. |
DT uses **nvmem-cells** / **nvmem-cell-names** (Linux-style). | MAC/calibration is hard-coded in BSP C sources. |
You want refcounted **rt_nvmem_cell** handles. | Direct MMIO in a single platform driver is enough. |
| Field | Role |
|---|---|
**reg_read / reg_write** | Byte access at **offset** |
**read_only** | DT **read-only**, no **reg_write**, or preset flag |
**wp_pin** | Optional **wp** GPIO for EEPROM |
**register**: optional **wp** pin, **read_only** from DT / missing **reg_write**, **rt_ofw_data(np)=ndev**.
**unregister**: only if **rt_ref_read(&ndev->ref)==1**.
**append_cell**: static cells (**free_able false**) known at probe time.
len <= cell->bytes** and **<= nvmem->size**bit_offset**, **nbits** — read shifts/masks; write read-modify-writewp_pin** deasserted during **reg_write**rt_nvmem_cell_read_u8/u16/u32/u64**| Issue | Mitigation |
|---|---|
Forgot **put_cell** | Blocks unregister |
| OTP write | Omit **reg_write** |
| No BSP provider | **SOC_DM_NVMEM_DIR** |
components/drivers/nvmem/Kconfig